[php-src] jit-arm64: Enable register allocator (it was disabled because ZREG_NUM wasn't

Author: Dmitry Stogov (dstogov) Date: 2021-04-27T01:25:35+03:00 Commit: https://github.com/php/php-src/commit/b6e632bb635d9b57996813e76b9ed3a842740b0b Raw diff: https://github.com/php/php-src/commit/b6e632bb635d9b57996813e76b9ed3a842740b0b.diff Enable register allocator (it was disabled because ZREG_NUM wasn't available for preprocessor) and fix few related problems. Changed paths: M ext/opcache/jit/zend_jit_arm64.dasc M ext/opcache/jit/zend_jit_arm64.h M ext/opcache/jit/zend_jit_internal.h M ext/opcache/jit/zend_jit_x86.h Diff: diff --git a/ext/opcache/jit/zend_jit_arm64.dasc b/ext/opcache/jit/zend_jit_arm64.dasc index 3255017f87cf..166e1481e92a 100644 --- a/ext/opcache/jit/zend_jit_arm64.dasc +++ b/ext/opcache/jit/zend_jit_arm64.dasc @@ -3123,9 +3123,24 @@ static int zend_jit_update_regs(dasm_State **Dst, uint32_t var, zend_jit_addr sr if (!zend_jit_same_addr(src, dst)) { if (Z_MODE(src) == IS_REG) { if (Z_MODE(dst) == IS_REG) { - | mov Rx(Z_REG(dst)), Rx(Z_REG(src)) + if ((info & MAY_BE_ANY) == MAY_BE_LONG) { + | mov Rx(Z_REG(dst)), Rx(Z_REG(src)) + } else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) { + | fmov Rd(Z_REG(dst)-ZREG_V0), Rd(Z_REG(src)-ZREG_V0) + } else { + ZEND_UNREACHABLE(); + } } else if (Z_MODE(dst) == IS_MEM_ZVAL) { - | fmov Rd(Z_REG(dst)-ZREG_V0), Rd(Z_REG(src)-ZREG_V0) + if (!Z_LOAD(src) && !Z_STORE(src)) { + if (!zend_jit_spill_store(Dst, src, dst, info, + JIT_G(trigger) != ZEND_JIT_ON_HOT_TRACE || + JIT_G(current_frame) == NULL || + STACK_MEM_TYPE(JIT_G(current_frame)->stack, EX_VAR_TO_NUM(var)) == IS_UNKNOWN || + (1 << STACK_MEM_TYPE(JIT_G(current_frame)->stack, EX_VAR_TO_NUM(var))) != (info & MAY_BE_ANY) + )) { + return 0; + } + } } else { ZEND_UNREACHABLE(); } @@ -3746,7 +3761,7 @@ static int zend_jit_math_double_double(dasm_State **Dst, } else if (Z_MODE(val_addr) == IS_REG) { op2_reg = Z_REG(val_addr); } else { - op2_reg = ZREG_FPR1; + op2_reg = ZREG_FPTMP; | GET_ZVAL_DVAL op2_reg, val_addr, ZREG_TMP1 } | DOUBLE_MATH_REG opcode, result_reg, op1_reg, op2_reg diff --git a/ext/opcache/jit/zend_jit_arm64.h b/ext/opcache/jit/zend_jit_arm64.h index c0a2cb901ecf..472598fa57b3 100644 --- a/ext/opcache/jit/zend_jit_arm64.h +++ b/ext/opcache/jit/zend_jit_arm64.h @@ -136,6 +136,8 @@ typedef struct _zend_jit_registers_buf { typedef uint64_t zend_regset; +#define ZEND_REGSET_64BIT 1 + # define ZEND_REGSET_FIXED \ (ZEND_REGSET(ZREG_RSP) | ZEND_REGSET(ZREG_RLR) | ZEND_REGSET(ZREG_RFP) | \ ZEND_REGSET(ZREG_RPR) | ZEND_REGSET(ZREG_FP) | ZEND_REGSET(ZREG_IP) | \ diff --git a/ext/opcache/jit/zend_jit_internal.h b/ext/opcache/jit/zend_jit_internal.h index 23c6cb3409c1..84a7e94d8a33 100644 --- a/ext/opcache/jit/zend_jit_internal.h +++ b/ext/opcache/jit/zend_jit_internal.h @@ -30,7 +30,7 @@ #define ZEND_REGSET_IS_SINGLETON(regset) \ (regset && !(regset & (regset - 1))) -#if (ZREG_NUM <= 32) +#if (!ZEND_REGSET_64BIT) #define ZEND_REGSET(reg) \ (1u << (reg)) #else @@ -38,7 +38,7 @@ (1ull << (reg)) #endif -#if (ZREG_NUM <= 32) +#if (!ZEND_REGSET_64BIT) #define ZEND_REGSET_INTERVAL(reg1, reg2) \ (((1u << ((reg2) - (reg1) + 1)) - 1) << (reg1)) #else @@ -65,14 +65,12 @@ ((set1) & ~(set2)) #if !defined(_WIN32) -# if (ZREG_NUM <= 32) +# if (!ZEND_REGSET_64BIT) # define ZEND_REGSET_FIRST(set) ((zend_reg)__builtin_ctz(set)) # define ZEND_REGSET_LAST(set) ((zend_reg)(__builtin_clz(set)^31)) -# elif(ZREG_NUM <= 64) +# else # define ZEND_REGSET_FIRST(set) ((zend_reg)__builtin_ctzll(set)) # define ZEND_REGSET_LAST(set) ((zend_reg)(__builtin_clzll(set)^63)) -# else -# error "Too many registers" # endif #else # include <intrin.h> diff --git a/ext/opcache/jit/zend_jit_x86.h b/ext/opcache/jit/zend_jit_x86.h index 5499103c1213..52ae8a98a701 100644 --- a/ext/opcache/jit/zend_jit_x86.h +++ b/ext/opcache/jit/zend_jit_x86.h @@ -114,6 +114,8 @@ typedef struct _zend_jit_registers_buf { typedef uint32_t zend_regset; +#define ZEND_REGSET_64BIT 0 + #ifdef _WIN64 # define ZEND_REGSET_FIXED \ (ZEND_REGSET(ZREG_RSP) | ZEND_REGSET(ZREG_R14) | ZEND_REGSET(ZREG_R15))